Correlations between Radiation Hardness and Variations of FFs Denpending on Layout Structures in a 28 nm Thin BOX FD-SOI Process by Alpha Particles Irradiation
نویسندگان
چکیده
We design three different layouts of DFFs in a 28 nm thin-BOX FD-SOI process to compare their radiation hardness. We measure them by alpha-particle irradiation. Experimental results show that the soft-error probability of two-fingered inverters is 2.6x higher than that of one-fingered one at 0.4 V when DATA and CLK are 1 and 0 respectively. We also measure the relationship between process variations and radiation hardness in each FF. The process variation affects retention voltage of FFs. FFs with higher retention voltage are more vulnerable to radiation than FFs with lower retention voltage.
منابع مشابه
Estimation of Soft Error Tolerance according to the Thickness of Buried Oxide and Body Bias 28-nm and 65-nm in FD-SOI Processes by a Monte-Carlo Simulation
1. Abstract We estimate the soft error rates of FD-SOI structures according to the thicknesses of BOX(Buird OXide) layers and body bias on 65-nm and 28-nm processes by reducing the supply voltage. A Monte-Carlo based simulation is used in this work. The parasitic bipolar effect is suppressed by thicker BOX on FD-SOI structure.The simulation results are consistent with the alpha and neutron irra...
متن کاملAnalysis of Terrestrial Single Event Upsets by Body Biases in a 28 nm UTBB Process by a PHITS-TCAD Simulation System
We analyze the soft-error tolerance of a latch in a 28-nm UTBB (Ultra Thin Body and BOX) process by a PHITS-TCAD simulation system. It is composed of two parts, a particle transport simulation by PHITS (Particle and Heavy Ion Transport code System) and a device simulation. The neutron induced SERs (soft error rates) can be analyzed by the simulation system. We investigate the soft errors on 28-...
متن کاملRadiation-hard Layout Structures on Bulk and SOI Process by Device-level Simulations
This paper analyze the soft error tolerance related to layout structures on 65-nm bulk and SOI processes. The layout structure in which well contacts are placed between redundant latches suppresses MCU effectively. Also the tolerance of SOI structure transistor is estimated by TCAD simulations. The charge collection mechanism is suppressed by the BOX (Buried Oxide) in SOI transistor. Charge sha...
متن کاملPreliminary study on the properties of zinc oxide (ZnO) for alpha particles detection
Background: : Due to the difficulties of locally obtaining ZnS(Ag), preliminary investigation of the radioluminescence characterization of Zinc oxide (ZnO) for alpha particle detection was performed. Materials and Methods: The scintillation properties of ZnO films were tested using alpha sources  ...
متن کاملLow voltage logic circuits exploiting gate level dynamic body biasing in 28nm UTBB FD-SOI
In this paper, the recently proposed gate level body bias (GLBB) technique is evaluated for low voltage logic design in state-of-the-art 28 nm ultra-thin body and box (UTBB) fully-depleted silicon-oninsulator (FD-SOI) technology. The inherent benefits of the low-granularity body-bias control, provided by the GLBB approach, are emphasized by the efficiency of forward body bias (FBB) in the FD-SO...
متن کامل